The present invention relates to a semiconductor apparatus having a chip size package used for a high density assembly module or a multi-chip module.
Recently, in association with wide spread of portable information terminal units and miniaturization and high performance of electronic devices, high density packing, high densification, and speeding up of processing are also required for a semiconductor device. In correspondence with it, as a semiconductor apparatus mounting method, a multi-pin corresponding type package such as from the pin insertion type to the surface mounting type and from a DIP (dual inline package) to a QFP (quad flat package) or PGA (pin grid array) has been developed.
However, in the QFP type, the connection lead wires with the mounting substrate are centralized in the peripheral part of the package and moreover the lead wires themselves are thin and deformable, so that as the number of pins increases, the mounting reliability reduces. In the PGA type, the terminals to be connected to the mounting substrate are long and thin and centralized extremely, so that speeding up is difficult on an electric characteristic basis.
To realize a semiconductor apparatus in correspondence with high speed, a package of a BGA (ball grid array) type having a stress cushioning material between the semiconductor element and the substrate with a wiring circuit formed and a bump electrode which is an external terminal on the mounting substrate surface side of the substrate with a wiring circuit formed has been proposed (U.S. Pat. No. 5,148,265).
In this package, surface mounting is available that the terminals for connecting with the mounting substrate are ball-shaped solder, and the lead wires are free of deformation such as generated in the QFP type, and the terminals can be dispersed overall the package surface, and the pitch between the terminals can be made longer. As compared with the PGA type, the bump electrode which is an external terminal is short in length, so that the inductance component is small and the signal transmission can be speeded up.
A CSP (chip scale package) having a size almost equal to that of the chip is disclosed in xe2x80x9cNikkei Microdevicexe2x80x9d issued by Nikkei BP, Ltd. (February 1998) (p. 38 to p. 64). In the CSP, on the polyimide or ceramics substrate with a wiring layer formed, semiconductor elements cut into pieces are adhered, and then the wiring layer and the semiconductor elements are electrically connected by wire bonding, single point bonding, gang bonding, or bump bonding, and the connections are sealed by resin, and then an external terminal such as a solder bump is formed.
Japanese Patent Application Laid-Open 9-232256 and Japanese Patent Application Laid-Open 10-27827 disclose methods for mass-producing CSPs. The methods form a bump on a semiconductor wafer, electrically connect a wiring substrate via the bump, then seal the connections with resin, form an external electrode on the wiring substrate, finally cut it into pieces, and manufacture a semiconductor apparatus. In xe2x80x9cNikkei Microdevicexe2x80x9d (p. 164 to 167) issued by Nikkei BP, Ltd. (April 1998), a bump is formed by plating on a semiconductor wafer and the part other than the bump is sealed by resin. Furthermore, an external electrode is formed in the bump part, and finally it is cut into pieces, and a semiconductor apparatus is manufactured.
In the CSP which is assembled by adhering the semiconductor elements cut into pieces to the aforementioned polyimide or ceramics substrate, when the wiring layer and chip are connected by wire bonding, since the bonding area of the wiring layer is positioned outside the bonding area, the package size is necessarily larger than the chip size. When they are connected by bump bonding, to prevent resin from dropping when the chip and substrate are sealed by bonding resin, the chip is larger than the substrate. Namely, a problem arises that the size of the CSP is larger than the chip size.
In the aforementioned CSP using chips cut into pieces, since the chips are diced and then each chip is positioned and adhered on the substrate, electrically connected, and sealed with resin, a problem arises that it requires a lot of time to manufacture a semiconductor apparatus.
In a CSP using a resin substrate such as polyimide or glass epoxy, the chips are adhered via an adhesive, so that a problem arises that at the time of reflow when the package is mounted on the mounting substrate, absorbed moisture is expanded inside the package and a fault such as foaming or peeling is caused.
In a CSP that a bump is formed on a semiconductor wafer, and the wafer is connected to the substrate, and resin is sealed between the substrate and the semiconductor wafer, and an external electrode is formed, and then the wafer is cut into pieces, a resin layer is formed only on one side of the wafer, so that a problem arises that the semiconductor wafer and semiconductor apparatus are warped due to cure shrinkage of the resin.
The present invention, with the foregoing in view, provides a miniature semiconductor apparatus for corresponding to high density packing, high densification, and speeding up of processing which is outstanding in mounting reliability and mass production.
The summary of the present invention for solving the aforementioned problems will be described hereunder.
(1) In a semiconductor apparatus having at least one stress cushioning layer on a semiconductor element with an electrode pad formed, having a conductor on the stress cushioning layer, having a conductor for conducting the electrode pad and conductor via a through hole passing through the stress cushioning layer between the electrode pad and the conductor, having an external electrode on the conductor, and having a stress cushioning layer in other than the area where the external electrode exists and a conductor protection layer on the conductor, the stress cushioning layer includes crosslinking acrylonitrile-butadiene rubber having an epoxy resin which is solid at 25xc2x0 C. and a carboxyl group.
The end faces of the semiconductor element of the semiconductor apparatus and of the stress cushioning layer or conductor protection layer are exposed outside on the same surface and the stress cushioning layer is a film-shaped adhesive including 100 to 200 wt % of fine particles of crosslinking acrylonitride-butadiene series having an epoxy resin composition which is solid at 25xc2x0 C. and a carboxyl group to 100 wt % of expoxy resin composition.
The aforementioned semiconductor apparatus is an apparatus that the end face of the stress cushioning layer or conductor protection layer is exposed outside on the inside of the end face of the semiconductor element.
(2) In a semiconductor apparatus having a semiconductor element protection layer on a semiconductor element with an electrode pad formed, having a first conductor on the semiconductor element protection layer, having a conductor for conducting the electrode pad and first conductor via a first through hole passing through the semiconductor element protection layer between the electrode pad and the first conductor, having a stress cushioning layer composed of a single or a plurality of layers on the semiconductor element protection layer and first conductor, having a second conductor on the stress cushioning layer, having a conductor for conducting the first conductor and second conductor via a second through hole passing through the stress cushioning layer between the first conductor and the second conductor, having an external electrode on the second conductor, having a stress cushioning layer in other than the area where the external electrode exists and a conductor protection layer on the second conductor, wherein the end faces of the semiconductor element, stress cushioning layer, and conductor protection layer are exposed outside on the same surface and the stress cushioning layer is a film-shaped adhesive including 100 to 200 wt % of crosslinking acrylonitride-butadiene rubber having an epoxy resin composition which is solid at 25xc2x0 C. and a carboxyl group to 100 wt % of expoxy resin composition.
(3) In a semiconductor apparatus having a semiconductor element protection layer on a semiconductor element with an electrode pad formed, having a first conductor on the semiconductor element protection layer, having a conductor for conducting the electrode pad and first conductor via a first through hole passing through the semiconductor element protection layer between the electrode pad and the first conductor, having a stress cushioning layer composed of a single or a plurality of layers on the semiconductor element protection layer and first conductor, having a second conductor on the stress cushioning layer, having a conductor for conducting the first conductor and second conductor via a second through hole passing through the stress cushioning layer between the first conductor and the second conductor, having an external electrode on the second conductor, having a stress cushioning layer in other than the area where the external electrode exists and a conductor protection layer on the second conductor, wherein the end faces of the semiconductor protection layer, stress cushioning layer, and conductor protection layer are exposed outside on the inside of the end face of the semiconductor element and the stress cushioning layer is a film-shaped adhesive including 100 to 200 wt % of fine particles of crosslinking acrylonitride-butadiene rubber having an epoxy resin composition which is solid at 25xc2x0 C. and a carboxyl group to 100 wt % of expoxy resin composition.